idxTmplt[24] = "S1L60k_port2_RTL_Veri" ;
tmplt[24] = [
  "// S1L60000 Sync. 2 port RAM RTL Simulation Library",
  "",
  "// SEIKO EPSON",
  "//#Ver. 1.0 2006/09/xx Mori, Masaru",
  "//#         Created",
  "//#Ver. 1.1 2006/10/11 Mori, Masaru",
  "//#         Correct the bug of endless loop",
  "//#Ver. 1.2 2006/10/20 Mori, Masaru",
  "//#         Correct the bug of not to keep addr. and data at CK is risen,",
  "//#           and to display non-exe... error if AB is X.",
  "//#Ver. 1.3 2006/10/23 Mori, Masaru",
  "//#         Delete \"D_OUT = 'hx\" at AA = x, because this is not async. RAM.",
  "//#         Changed \"!=\" to \"!==\"",
  "//#Ver. 1.4 2006/10/31 Mori, Masaru",
  "//#         Add the function for CK = X",
  "//#Ver. 1.5 2006/11/02 Mori, Masaru",
  "//#         Change as Y is through if XRB = 0",
  "//#Ver. 1.6 2006/11/06 Mori, Masaru",
  "//#         Make X if AB(XRB=0) = AA(XWA=0)",
  "// Ver. 1.7 2007/09/xx Mori, Masaru",
  "//#         Use new keywords.",
  "//#         Make same as VHDL 1.0",
  "",
  "module %CellName% ( CKA, XWA,",
  "                 %EachAddr , AA%,",
  "                 %EachData , D%,",
  "                 CKB, XRB,",
  "                 %EachAddr , AB%,",
  "                 %EachData , Y% );",
  "",
  "  parameter depth = %Depth% ;",
  "  parameter addr_width = %WidthAddr% ;",
  "  parameter data_width = %WidthData% ;",
  "",
  "  input CKA, XWA ;",
  "  input %EachAddr , AA% ;",
  "  input %EachData , D% ;",
  "  input CKB, XRB ;",
  "  input %EachAddr , AB% ;",
  "  output %EachData , Y% ;",
  "",
  "  reg [data_width-1:0] mem [depth-1:0] ;",
  "",
  "  wire [addr_width-1:0] AddrA, AddrB ;",
  "  wire [data_width-1:0] D_IN ;",
  "  reg [data_width-1:0] D_OUT ;",
  "",
  "  reg [addr_width-1:0] regA, regB ;  // registers for Addr.",
  "  reg regXWA, regXRB ;               // registers for XWA and XRB",
  "  reg [addr_width:0] tmpADDR ;  // to write x to all addr. One bit bigger",
  "",
  "  assign AddrA = { %EachAddr , AA% };",
  "  assign D_IN = { %EachData , D% };",
  "  assign AddrB = { %EachAddr , AB% };",
  "  assign { %EachData , Y% } = D_OUT ;",
  "",
  "  //--- Write function --------------------------------------------------------",
  "  always @( CKA )begin",
  "    if( CKA == 1'b1 )begin",
  "      regXWA = XWA ;",
  "      regA = AddrA ;",
  "",
  "      if( XWA == 1'b0 )begin  //--- Write mode (clean) ---",
  "        if( AddrA == AddrA )begin  //--- addr. is not x ---",
  "          if( AddrA < depth )begin",
  "            mem[AddrA] = D_IN ;",
  "",
  "          end else begin",
  "            $display( \"RAM Warning(at %t)! non-existing RAM wr. address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin //--- if addr. is x, write x to all addr. ---",
  "          for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "            mem[tmpADDR] = 'hx ;",
  "          end",
  "        end",
  "",
  "      end else if( XWA !== 1'b1 )begin  //--- probably write ---",
  "        if( AddrA == AddrA )begin  //--- addr. is not x ---",
  "          if( AddrA < depth )begin",
  "            mem[AddrA] = 'hx ;",
  "",
  "          end else begin",
  "            $display( \"RAM Warning(at %t)! non-existing RAM wr. address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin //--- addr. is x ---",
  "          for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "            mem[tmpADDR] = 'hx ;",
  "          end",
  "        end",
  "      end",
  "",
  "    //--- CKA == X -------------------------------------------------------------",
  "    end else if( CKA !== 1'b0 )begin",
  "      if( XWA !== regXWA )begin",
  "        regXWA = 1'bx ;",
  "      end",
  "",
  "      if( (AddrA == AddrA) && (regA == regA) )begin  //--- addr. is not x ---",
  "        if( AddrA !== regA )begin",
  "          regA = 'hx ;",
  "        end",
  "      end else begin",
  "        regA = 'hx ;",
  "      end",
  "",
  "      if( XWA !== 1'b1 )begin  //--- probably write ---",
  "        if( AddrA == AddrA )begin  //--- addr. is not x ---",
  "          if( AddrA < depth )begin",
  "            mem[AddrA] = 'hx ;",
  "",
  "          end else begin",
  "            $display( \"RAM Warning(at %t)! non-existing RAM wr. address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin //--- if addr. is x, write x to all addr. ---",
  "          for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "            mem[tmpADDR] = 'hx ;",
  "          end",
  "        end",
  "      end",
  "    end",
  "  end",
  "",
  "  //--- Pre-read --------------------------------------------------------------",
  "  always @( CKB )begin",
  "    if( CKB == 1'b1 )begin",
  "      regXRB = XRB ;",
  "      regB = AddrB ;",
  "",
  "    end else if( CKB !== 1'b0 )begin",
  "      regXRB = 1'bx ;",
  "      regB = 'hx ;",
  "    end",
  "  end",
  "",
  "  //--- Read function ---------------------------------------------------------",
  "  always @( regXRB, regB, regXWA, regA )begin",
  "    if( regXRB == 1'b0 )begin",
  "      if( regB == regB )begin",
  "        if( regB < depth )begin //-- check if AB == AA if AB is clean --",
  "          if( regXWA !== 1'b1 )begin",
  "            if( regA == regA )begin",
  "              if( regB == regA )begin",
  "                D_OUT = 'hx ;",
  "              end else begin",
  "                D_OUT = mem[regB] ;",
  "              end",
  "            end else begin //-- If AA include X, may be AB is the same as AA --",
  "              D_OUT = 'hx ;",
  "            end",
  "",
  "          end else begin //-- Don't care AA, because not writing --",
  "            D_OUT = mem[regB] ;",
  "          end",
  "",
  "        end else begin",
  "          D_OUT = 'hx ;",
  "          if( AddrB == AddrB )begin  //--- addr. is not x ---",
  "            $display( \"RAM Warning(at %t)! non-existing RAM rd. address is accessed.\", $time );",
  "          end",
  "        end",
  "",
  "      end else begin  //-- Latched AB include X --",
  "        D_OUT = 'hx ;",
  "      end",
  "",
  "    end else if( XRB !== 1'b1 )begin",
  "      D_OUT = 'hx ;",
  "    end",
  "  end",
  "",
  "endmodule" ];