idxTmplt[20] = "S1L60k_port1_RTL_Veri" ;
tmplt[20] = [
  "// S1L60000 Sync. 1 port RAM RTL Simulation Library",
  "",
  "// SEIKO EPSON",
  "//#Ver. 1.0 2006/09/xx Mori, Masaru",
  "//#         Created",
  "//#Ver. 1.1 2006/10/11 Mori, Masaru",
  "//#         Correct the bug of endless loop",
  "//#Ver. 1.2 2006/10/31 Mori, Masaru",
  "//#         Add the function for CK = X",
  "// Ver. 1.3 2007/08/xx Mori, Masaru",
  "//#         Use new keywords.",
  "//#         Add checking ADDR depth when XWE == x",
  "",
  "module %CellName% ( CK, XCS, XWE,",
  "                 %EachAddr , A%,",
  "                 %EachData , D%,",
  "                 %EachData , Y% );",
  "",
  "  parameter depth = %Depth% ;",
  "  parameter addr_width = %WidthAddr% ;",
  "  parameter data_width = %WidthData% ;",
  "",
  "  input CK, XCS, XWE ;",
  "  input %EachAddr , A% ;",
  "  input %EachData , D% ;",
  "  output %EachData , Y% ;",
  "",
  "  reg [data_width-1:0] mem [depth-1:0] ;",
  "",
  "  wire [addr_width-1:0] ADDR ;",
  "  reg [addr_width:0] tmpADDR ;  // to write x to all addr. One bit bigger",
  "  wire [data_width-1:0] D_IN ;",
  "  reg [data_width-1:0] D_OUT ;",
  "",
  "  assign ADDR = { %EachAddr , A% };",
  "  assign D_IN = { %EachData , D% };",
  "  assign { %EachData , Y% } = D_OUT ;",
  "",
  "  always @( CK )begin",
  "    if( CK == 1'b1 )begin",
  "      //--- XCS is active -----------------------------------------------------",
  "      if( XCS == 1'b0 )begin",
  "        if( XWE == 1'b0 )begin  //--- Write mode (clean) ---",
  "          if( ADDR == ADDR )begin  //--- addr. is not x ---",
  "            if( ADDR < depth )begin",
  "              mem[ADDR] = D_IN ;",
  "              D_OUT = D_IN ;",
  "",
  "            end else begin",
  "              D_OUT = 'hx ;",
  "              $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "            end",
  "",
  "          end else begin //--- if addr. is x, write x to all addr. ---",
  "            for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "              mem[tmpADDR] = 'hx ;",
  "            end",
  "            D_OUT = 'hx ;",
  "          end",
  "",
  "        end else if( XWE == 1'b1 )begin  //--- Read mode (clean) ---",
  "          if( ADDR < depth )begin",
  "            D_OUT = mem[ADDR] ;",
  "",
  "          end else begin",
  "            D_OUT = 'hx ;",
  "            $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin  //--- XWE == x ---",
  "          D_OUT = 'hx ;",
  "          if( ADDR == ADDR )begin  //--- addr. is not x ---",
  "            if( ADDR < depth )begin",
  "              mem[ADDR] <= 'hx ;",
  "",
  "            end else begin",
  "              $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "            end",
  "",
  "          end else begin //--- addr. is x ---",
  "            for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "              mem[tmpADDR] = 'hx ;",
  "            end",
  "          end",
  "        end",
  "",
  "      //--- XCS is x ----------------------------------------------------------",
  "      end if( XCS === 1'bx )begin",
  "        D_OUT = 'hx ;",
  "        if( XWE == 1'b0 )begin  //--- Write mode (XCS=x) ---",
  "          if( ADDR == ADDR )begin  //--- addr. is not x ---",
  "            if( ADDR < depth )begin",
  "              mem[ADDR] = 'hx ;",
  "",
  "            end else begin",
  "              $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "            end",
  "",
  "          end else begin //--- addr. is x ---",
  "            for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "              mem[tmpADDR] = 'hx ;",
  "            end",
  "          end",
  "",
  "        end else if( XWE == 1'b1 )begin  //--- Read mode ---",
  "          if( ADDR < depth )begin",
  "",
  "          end else begin",
  "            $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin  //--- XWE == x ---",
  "          if( ADDR == ADDR )begin  //--- addr. is not x ---",
  "            if( ADDR < depth )begin",
  "              mem[ADDR] <= 'hx ;",
  "",
  "            end else begin",
  "              $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "            end",
  "",
  "          end else begin //--- addr. is x ---",
  "            for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "              mem[tmpADDR] = 'hx ;",
  "            end",
  "          end",
  "        end",
  "      end",
  "",
  "    //--- CK == X -------------------------------------------------------------",
  "    end else if( CK !== 0 )begin",
  "      //--- XCS may be active -------------------------------------------------",
  "      if( XCS !== 1'b1 )begin",
  "        D_OUT = 'hx ;",
  "",
  "        if( XWE !== 1'b1 )begin  //--- Write mode (CK = X) ---",
  "          if( ADDR == ADDR )begin  //--- addr. is not x ---",
  "            if( ADDR < depth )begin",
  "              mem[ADDR] = 'hx ;",
  "",
  "            end else begin",
  "              $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "            end",
  "",
  "          end else begin //--- if addr. is x, write x to all addr. ---",
  "            for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "              mem[tmpADDR] = 'hx ;",
  "            end",
  "          end",
  "",
  "        end else begin  //--- Read mode (CK = X) ---",
  "          if( ADDR < depth )begin",
  "          end else begin",
  "            $display( \"RAM Warning(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "        end",
  "      end",
  "    end",
  "  end",
  "",
  "endmodule" ];