idxTmplt[17] = "S1L50k_port2_Syn_VHDL" ;
tmplt[17] = [
  "-- S1L50000 Synchronous 2 port RAM library for Logic synthesis",
  "--  * No latch at output to hold the data when XCS = 1.",
  "--  * This Synchronous RAM is made with Asynchronous RAM + registers + gates.",
  "--",
  "-- SEIKO EPSON",
  "-- Ver. 1.0 2007/08/xx Mori, Masaru",
  "--#         Created.",
  "",
  "library IEEE ;",
  "use IEEE.std_logic_1164.all ;",
  "",
  "entity %CellName% is",
  "  generic( ADDR_W : integer := %WidthAddr% ;  -- Address width",
  "           DATA_W : integer := %WidthData% );  -- Data width",
  "",
  "  port( FCS, CKA, XWA, CKB, XRB : in  std_logic ;",
  "        %EachAddr , AA% : in  std_logic ;",
  "        %EachData , D% : in  std_logic ;",
  "        %EachAddr , AB% : in  std_logic ;",
  "        %EachData , Y% : out std_logic );",
  "end %CellName% ;",
  "",
  "architecture rtl of %CellName% is",
  "  component %RAMCell%",
  "    port( CS, WR, RD : in  std_logic ;",
  "          %EachAddrFull , WA% : in  std_logic ;",
  "          %EachDataFull , D% : in  std_logic ;",
  "          %EachAddrFull , RA% : in  std_logic ;",
  "          %EachDataFull , Y% : out std_logic );",
  "  end component ;",
  "",
  "  component DL2",
  "    port( A : in  std_logic ;",
  "          X : out std_logic );",
  "  end component ;",
  "",
  "  signal RegXWA, RegRB : std_logic ;",
  "  signal WA, RA : std_logic_vector( ADDR_W - 1 downto 0 );",
  "  signal D : std_logic_vector( DATA_W - 1 downto 0 );",
  "  signal N_CKDL, N_WR : std_logic ;",
  "",
  "  signal tie0 : std_logic ;",
  "  signal tie1 : std_logic ;",
  "",
  "begin",
  "  WR_PRC: process( CKA )",
  "  begin",
  "    if( CKA'event and CKA = '1' )then",
  "      RegXWA <= XWA ;",
  "      WA <= %EachAddr & AA% ;",
  "%OneBitData%      D(0) <= D0 ;",
  "%MulBitData%      D <= %EachData & D% ;",
  "    end if ;",
  "  end process ;",
  "",
  "  RD_PRC: process( CKB )",
  "  begin",
  "    if( CKB'event and CKB = '1' )then",
  "      RegRB <= not XRB ;",
  "      RA <= %EachAddr & AB% ;",
  "    end if ;",
  "  end process ;",
  "",
  "  tie0 <= '0' ;",
  "  tie1 <= '1' ;",
  "",
  "  I_CKDL: DL2 port map( A => CKA, X => N_CKDL );",
  "  N_WR <= not( RegXWA or not N_CKDL );",
  "",
  "  I_RAM: %RAMCell% port map(",
  "          CS => FCS, WR => N_WR,",
  "          %MapAddr VHDL WA 0%,",
  "          %MapData VHDL D 1%,",
  "          RD => RegRB,",
  "          %MapAddr VHDL RA 0%,",
  "          %MapDataNB VHDL Y% );",
  "end rtl ;" ];