idxTmplt[16] = "S1L50k_port2_Syn_Veri" ;
tmplt[16] = [
  "// S1L50000 Synchronous 2 port RAM library for Logic synthesis",
  "//  * No latch at output to hold the data when XCS = 1.",
  "//  * This Synchronous RAM is made with Asynchronous RAM + registers + gates.",
  "",
  "// SEIKO EPSON",
  "//#Ver. 1.0 2006/09/xx Mori, Masaru",
  "//#         Created.",
  "// Ver. 1.1 2007/08/xx Mori, Masaru",
  "//#         Use new keyword.",
  "",
  "module %CellName% ( FCS, CKA, XWA,",
  "                 %EachAddr , AA%,",
  "                 %EachData , D%,",
  "                 CKB, XRB,",
  "                 %EachAddr , AB%,",
  "                 %EachData , Y% );",
  "",
  "  parameter depth = %Depth% ;",
  "  parameter addr_width = %WidthAddr% ;",
  "  parameter data_width = %WidthData% ;",
  "",
  "  input FCS, CKA, XWA ;",
  "  input %EachAddr , AA% ;",
  "  input %EachData , D% ;",
  "  input CKB, XRB ;",
  "  input %EachAddr , AB% ;",
  "  output %EachData , Y% ;",
  "",
  "  reg RegXWA, RegXRB ;",
  "  reg [addr_width -1 : 0] WA, RA ;",
  "  reg [data_width -1 : 0] D ;",
  "  wire N_CKDL, N_WR ;",
  "",
  "  DL2 I_CKDL ( .A( CKA ), .X( N_CKDL ) );",
  "  assign N_WR = !( RegXWA | ~N_CKDL );",
  "",
  "  always @( posedge CKA )begin  // Register func. for the port-A (write port)",
  "    RegXWA <= XWA ;",
  "    WA <= { %EachAddr , AA% };",
  "    D <= { %EachData , D% };",
  "  end",
  "",
  "  always @( posedge CKB )begin  // Register func. for the port-B (read port)",
  "    RegXRB <= XRB ;",
  "    RA <= { %EachAddr , AB% };",
  "  end",
  "",
  "  %RAMCell% I_ASRAM ( .CS( FCS ),",
  "      .WR( N_WR ),",
  "      %MapAddr Ver WA 0%,",
  "      %MapData Ver D 1%,",
  "      .RD( ~RegXRB ),",
  "      %MapAddr Ver RA 0%,",
  "      %MapDataNB Ver Y% );",
  "",
  "endmodule" ];