idxTmplt[14] = "S1L50k_port2_RTL_Veri" ;
tmplt[14] = [
  "// S1L50000 Sync. 2 port RAM RTL Simulation Library",
  "// * Actual module is soft-macro by using Asynchronous RAM",
  "// * Output is not kept when XRB = 1.",
  "// * Function might not correct if FCS is not kept 1.",
  "",
  "// SEIKO EPSON",
  "//#Ver. 1.0 2006/09/xx Mori, Masaru",
  "//#         Created",
  "//#Ver. 1.1 2006/10/11 Mori, Masaru",
  "//#         Correct the bug of endless loop",
  "//#Ver. 1.2 2006/10/20 Mori, Masaru",
  "//#         Correct the bug of not to keep addr. and data at CK is risen,",
  "//#           and to display non-exe... error if AB is X.",
  "//#Ver. 1.3 2006/10/23 Mori, Masaru",
  "//#         Change \"!=\" to \"!==\"",
  "//#Ver. 1.4 2006/10/24 Mori, Masaru",
  "//#         Made to allow the same address write and read",
  "//#         Fixed the bug of writing when the addr. is reading.",
  "//#Ver. 1.5 2006/10/31 Mori, Masaru",
  "//#         Add the function of CK = X",
  "//#Ver. 1.6 2006/11/06 Mori, Masaru",
  "//#         Add not all X if CK == X and XWA !== 0",
  "//#Ver. 1.7 2006/11/06 Mori, Masaru",
  "//#         Delete \"#1\" at read, because unnecessary",
  "// Ver. 1.8 2007/08/xx Mori, Masaru",
  "//#         Use new keywords.",
  "//#         Change CKA to CKB at \"else if\" in \"always @( CKB )\"",
  "//#         Add the checking ADDR < depth when writing and XWA or FCS is \"X\".",
  "",
  "module %CellName% ( FCS, CKA, XWA,",
  "                 %EachAddr , AA%,",
  "                 %EachData , D%,",
  "                 CKB, XRB,",
  "                 %EachAddr , AB%,",
  "                 %EachData , Y% );",
  "",
  "  parameter depth = %Depth% ;",
  "  parameter addr_width = %WidthAddr% ;",
  "  parameter data_width = %WidthData% ;",
  "",
  "  input FCS ;  // Force CS (to turn off asynchronous CS directly)",
  "  input CKA, XWA ;",
  "  input %EachAddr , AA% ;",
  "  input %EachData , D% ;",
  "  input CKB, XRB ;",
  "  input %EachAddr , AB% ;",
  "  output %EachData , Y% ;",
  "",
  "  reg [data_width-1:0] mem [depth-1:0] ;",
  "",
  "  wire [addr_width-1:0] AddrA, AddrB ;",
  "  wire [data_width-1:0] D_IN ;",
  "  reg [data_width-1:0] D_OUT ;",
  "",
  "  reg [addr_width-1:0] regB ;   // to keep AddrB at CK is risen",
  "  reg [addr_width:0] tmpADDR ;  // to write x to all addr. One bit bigger",
  "",
  "  assign AddrA = { %EachAddr , AA% };",
  "  assign D_IN = { %EachData , D% };",
  "  assign AddrB = { %EachAddr , AB% };",
  "  assign { %EachData , Y% } = (FCS == 1'b1)? D_OUT : 'bx ;",
  "",
  "  //--- Write function --------------------------------------------------------",
  "  always @( CKA )begin",
  "    if( CKA == 1'b1 )begin",
  "      if( (XWA == 1'b0) && (FCS == 1'b1) )begin  //--- Write mode (clean) ---",
  "        if( AddrA == AddrA )begin  //--- addr. is not x ---",
  "          if( AddrA < depth )begin",
  "            mem[AddrA] = D_IN ;",
  "",
  "          end else begin",
  "            $display( \"RAM Error(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin //--- if addr. is x, write x to all addr. ---",
  "          for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "            mem[tmpADDR] = 'hx ;",
  "          end",
  "        end",
  "",
  "      end else if( (XWA !== 1'b1) && (FCS !== 1'b0) )begin  //--- XWA or FCS == x ---",
  "        if( AddrA == AddrA )begin  //--- addr. is not x ---",
  "          if( AddrA < depth )begin",
  "            mem[AddrA] = 'hx ;",
  "",
  "          end else begin",
  "            $display( \"RAM Error(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "",
  "        end else begin //--- addr. is x ---",
  "          for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "            mem[tmpADDR] = 'hx ;",
  "          end",
  "        end",
  "      end",
  "",
  "    end else if( CKA !== 1'b0 )begin  // CK == X",
  "      if( XWA !== 1'b1 )begin",
  "        for( tmpADDR = 0; tmpADDR < depth; tmpADDR = tmpADDR + 1 )begin",
  "          mem[tmpADDR] = 'hx ;",
  "        end",
  "      end",
  "    end",
  "  end",
  "",
  "  //--- Read function ---------------------------------------------------------",
  "  always @( CKB )begin",
  "    if( CKB == 1'b1 )begin",
  "      if( (XRB == 1'b0) && (FCS == 1'b1) )begin  //--- Read mode (clean) ---",
  "        if( AddrB < depth )begin",
  "          regB = AddrB ;",
  "          assign D_OUT = mem[regB] ;",
  "            // assign is to read the written data, even if no CKB",
  "",
  "        end else begin",
  "          assign D_OUT = 'hx ;",
  "          if( AddrB == AddrB )begin  //--- addr. is not x: AddrB >= depth ---",
  "            $display( \"RAM Error(at %t)! non-existing RAM address is accessed.\", $time );",
  "          end",
  "        end",
  "",
  "      end else begin  //--- XRB == 1 or X, or FCS == 0 or X ---",
  "        assign D_OUT = 'hx ;",
  "      end",
  "",
  "    end else if( CKB !== 1'b0 )begin  // CK == X",
  "      assign D_OUT = 'hx ;",
  "    end",
  "  end",
  "",
  "endmodule" ];