idxTmplt[10] = "S1L50k_port1_Syn_Veri" ;
tmplt[10] = [
  "// S1L50000 Synchronous 1 port RAM library for Logic synthesis",
  "// no latch at output to hold the data when XCS = 1.",
  "//   This Synchronous RAM is made with Asynchronous RAM + registers + gates.",
  "",
  "// SEIKO EPSON",
  "//#Ver. 1.0 2006/09/xx Mori, Masaru",
  "//#         Created.",
  "// Ver. 1.1 2007/08/xx Mori, Masaru",
  "//#         Use new keyword.",
  "",
  "module %CellName% ( CK, XCS, XWE, FCS,",
  "                 %EachAddr , A%,",
  "                 %EachData , D%,",
  "                 %EachData , Y% );",
  "",
  "  parameter depth = %Depth% ;",
  "  parameter addr_width = %WidthAddr% ;",
  "  parameter data_width = %WidthData% ;",
  "",
  "  input CK, XCS, XWE ;",
  "  input FCS ;  // FCS is Force CS to disable RAM, directly. (for Iddq Test)",
  "  input %EachAddr , A% ;",
  "  input %EachData , D% ;",
  "  output %EachData , Y% ;",
  "",
  "  reg RegXWE, RegCS ;",
  "  reg [addr_width -1 : 0] A ;",
  "  reg [data_width -1 : 0] D ;",
  "  wire N_CKDL, N_RW, N_CS ;",
  "",
  "  DL2 I_CKDL ( .A( CK ), .X( N_CKDL ) );",
  "  assign N_RW = RegXWE | ~N_CKDL ;",
  "",
  "  assign N_CS = RegCS & FCS ;",
  "",
  "  always @( posedge CK )begin  // Register func. for the input signals",
  "    RegCS <= ~XCS ;",
  "    RegXWE <= XWE ;",
  "    A <= { %EachAddr , A% };",
  "    D <= { %EachData , D% };",
  "  end",
  "",
  "  %RAMCell% I_ASRAM (",
  "      .CS( N_CS ), .RW( N_RW ),",
  "      %MapAddr Ver A 0%,",
  "      %MapData Ver D 1%,",
  "      %MapDataNB Ver Y% );",
  "",
  "endmodule" ];