idxTmplt[9] = "S1L50k_port1_RTL_VHDL" ;
tmplt[9] = [
  "-- S1L50000 Sync. 1 port RAM RTL Simulation Library",
  "-- * This model does not latch the last data when XCS = 1.",
  "-- * Actual module is soft-macro by using Asynchronous RAM",
  "-- * Function might not correct if FCS is not kept 1.",
  "",
  "-- Note. If CK is changed to X, all written data become X.",
  "",
  "-- SEIKO EPSON",
  "-- Ver. 1.0 2007/09/xx Mori, Masaru",
  "--#         Created.",
  "",
  "library IEEE ;",
  "use IEEE.std_logic_1164.all ;",
  "use IEEE.STD_LOGIC_UNSIGNED.ALL ;",
  "use IEEE.std_logic_textio.all ;",
  "use std.textio.all ;",
  "",
  "entity %CellName% is",
  "  generic( DEPTH : integer := %Depth% ;",
  "           ADDR_W : integer := %WidthAddr% ;   -- Address width",
  "           DATA_W : integer := %WidthData% );  -- Data width",
  "",
  "  port( FCS, CK, XCS, XWE : in  std_logic ;",
  "        %EachAddr , A% : in  std_logic ;",
  "        %EachData , D% : in  std_logic ;",
  "        %EachData , Y% : out  std_logic );",
  "end %CellName% ;",
  "",
  "architecture behavior of %CellName% is",
  "",
  "  subtype WORD is std_logic_vector( DATA_W - 1 downto 0 );",
  "  type MEMORY is array ( 0 to DEPTH - 1 ) of WORD ;",
  "  signal MEM : MEMORY ;",
  "",
  "  signal ADDR : std_logic_vector( ADDR_W - 1 downto 0 );",
  "  signal DT_WR : std_logic_vector( DATA_W - 1 downto 0 );",
  "  signal DT_RD : std_logic_vector( DATA_W - 1 downto 0 );",
  "",
  "  signal RegXCS, RegXWE : std_logic ;",
  "  signal RegADDR : std_logic_vector( ADDR_W - 1 downto 0 );",
  "",
  "begin",
  "  ADDR <= %EachAddr & A% ;",
  "%OneBitData%  DT_WR(0) <= D0 ;",
  "%MulBitData%  DT_WR <= %EachData & D% ;",
  "%LineData%  Y%IndexData% <= DT_RD(%IndexData%) when FCS = '1' else 'X' ;",
  "",
  "  process( CK )",
  "    variable IDX : integer ;  -- Index (Integer of ADDR)",
  "    variable XJUDGE : std_logic ;  -- if ADDR include 'X', this is 'X'",
  "    variable WR_LINE : line ;  -- to write error message",
  "  begin",
  "    -- Rise --",
  "    if( CK'event and CK = '1' )then",
  "      RegXCS <= XCS ;    -- for write after read function at CK falling",
  "      RegXWE <= XWE ;    --  /",
  "      RegADDR <= ADDR ;  -- /",
  "",
  "      -- Check if ADDR include 'X' --",
  "      XJUDGE := ADDR(0) ;",
  "      for IDX in 1 to ADDR_W - 1 loop",
  "        XJUDGE := XJUDGE xor ADDR( IDX );",
  "      end loop ;",
  "",
  "      -- XCS is active --",
  "      if( XCS = '0' )then",
  "        -- Write --",
  "        if( (XWE = '0') and (FCS = '1') )then",
  "          -- normal Write (ADDR is clean) --",
  "          if( (XJUDGE = '0') or (XJUDGE = '1') )then",
  "            if( conv_integer( ADDR ) < DEPTH )then",
  "              MEM( conv_integer( ADDR ) ) <= DT_WR ;",
  "              DT_RD <= ( others => 'X' );",
  "",
  "            else",
  "              DT_RD <= ( others => 'X' );",
  "              write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "              write( WR_LINE, now );",
  "              write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "              writeline( output, WR_LINE );",
  "            end if ;",
  "",
  "          -- ADDR include 'X' --",
  "          else",
  "            for I in 0 to DEPTH - 1 loop",
  "              MEM( I ) <= ( others => 'X' );",
  "            end loop ;",
  "            DT_RD <= ( others => 'X' );",
  "          end if ;",
  "",
  "        -- Read --",
  "        elsif( XWE = '1' )then",
  "          if( conv_integer( ADDR ) < depth )then",
  "            DT_RD <= MEM( conv_integer( ADDR ) );",
  "",
  "          else",
  "            DT_RD <= ( others => 'X' );",
  "            write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "            write( WR_LINE, now );",
  "            write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "            writeline( output, WR_LINE );",
  "          end if ;",
  "",
  "        -- XWE is 'X' --",
  "        elsif( FCS /= '0' )then",
  "          -- ADDR is clean --",
  "          if( (XJUDGE = '0') or (XJUDGE = '1') )then",
  "            if( conv_integer( ADDR ) < depth )then",
  "              MEM( conv_integer( ADDR ) ) <= ( others => 'X' );",
  "              DT_RD <= ( others => 'X' );",
  "            else",
  "              DT_RD <= ( others => 'X' );",
  "              write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "              write( WR_LINE, now );",
  "              write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "              writeline( output, WR_LINE );",
  "            end if ;",
  "",
  "          -- ADDR include 'X' --",
  "          else",
  "            for I in 0 to DEPTH - 1 loop",
  "              MEM( I ) <= ( others => 'X' );",
  "            end loop ;",
  "            DT_RD <= ( others => 'X' );",
  "          end if ;",
  "        end if ;",
  "",
  "      -- XCS is '1' --",
  "      elsif( XCS = '1' )then",
  "        DT_RD <= ( others => 'X' );",
  "",
  "      -- XCS is 'X' --",
  "      elsif( XCS = 'X' )then",
  "        DT_RD <= ( others => 'X' );",
  "        -- probably Write --",
  "        if( (XWE = '0') and (FCS = '1' ) )then",
  "",
  "          -- ADDR is clean --",
  "          if( (XJUDGE = '0') or (XJUDGE = '1') )then",
  "            if( conv_integer( ADDR ) < DEPTH )then",
  "              MEM( conv_integer( ADDR ) ) <= ( others => 'X' );",
  "            else",
  "              write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "              write( WR_LINE, now );",
  "              write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "              writeline( output, WR_LINE );",
  "            end if ;",
  "",
  "          -- ADDR include 'X' --",
  "          else",
  "            for I in 0 to DEPTH - 1 loop",
  "              MEM( I ) <= ( others => 'X' );",
  "            end loop ;",
  "          end if ;",
  "",
  "        -- probably Read ---",
  "        elsif( XWE = '1' )then",
  "          if( conv_integer( ADDR ) < DEPTH )then",
  "          else",
  "            write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "            write( WR_LINE, now );",
  "            write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "            writeline( output, WR_LINE );",
  "          end if ;",
  "",
  "        -- XWE is 'X' --",
  "        elsif( FCS /= '0' )then",
  "          -- ADDR is clean --",
  "          if( (XJUDGE = '0') or (XJUDGE = '1') )then",
  "            if( conv_integer( RegADDR ) < depth )then",
  "              MEM( conv_integer( ADDR ) ) <= ( others => 'X' );",
  "            else",
  "              write( WR_LINE, string'( \"RAM Error(at \" ) );",
  "              write( WR_LINE, now );",
  "              write( WR_LINE, string'( \")! non-existing RAM address is accessed.\" ) );",
  "              writeline( output, WR_LINE );",
  "            end if ;",
  "",
  "          -- ADDR include 'X' --",
  "          else",
  "            for I in 0 to DEPTH - 1 loop",
  "              MEM( I ) <= ( others => 'X' );",
  "            end loop ;",
  "          end if ;",
  "        end if ;",
  "",
  "      end if ;  -- XCS",
  "",
  "    -- When CK is fallen, write after read function is occurred --",
  "    elsif( CK'event and CK = '0' )then",
  "      if( (RegXCS = '0') and (RegXWE = '0')",
  "           and ((XJUDGE = '0') or (XJUDGE = '1')) )then",
  "        if( conv_integer( RegADDR ) < depth )then",
  "          DT_RD <= MEM( conv_integer( RegADDR ) );",
  "",
  "        else",
  "          DT_RD <= ( others => 'X' );",
  "        end if ;",
  "      end if ;",
  "",
  "    -- If CK is X, All asynchronous signals are X --",
  "    else",
  "      for I in 0 to DEPTH - 1 loop",
  "        MEM( I ) <= ( others => 'X' );",
  "      end loop ;",
  "      DT_RD <= ( others => 'X' );",
  "    end if ;  -- CK",
  "  end process ;",
  "end behavior ;" ];