Semiconductors


Products: ASIC [Embedded Arrays]

Creating hard macros for cells that are highly integrated and have advanced functionality enable development of system-on-a-chip designs, and utilization of the sea-of-gates structure in the logic means that development period subsequent to the interconnection process is roughly equivalent to that for gate array chip.
In addition, the base bulk for LSI can bi reused allowing only the logic block to be modified in development lead time equivalent to that for gate array chips.
Embedded array technology also facilitates circuit design changes and thereby helps avoid the risks associated with product modifications

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Design for Embedded Array Chips

Design of embedded array chips begins with system design, during which the gate count and macro cells in the logic block are determined. Next, the base wafer is fabricated. Hard macros (macro cells) are then implemented on the base wafer and the sea-ofgates logic block is formed as fabrication proceeds as far as the interconnection process. As is also the case with gate arrays, concurrent with these fabrication operations designers carry out the steps from logic block circuit design to post-layout simulation fixes, after which comes the sign-off step before proceeding to the interconnection layout process. After sign-off, samples are shipped on a delivery schedule similar to that for gate arrays. Since the base bulk for LSI can be reused, modifications of the logic block only can be made using development costs and development lead time equivalent to those for gate arrays.

Design for Embedded Array Chips
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Embedded Array Lineup

S1X70000Series

Status MP
Manual

S1K70000/S1X70000 Series 5V Tolerant Design Guide (5,390kb)

S1K70000/S1X70000 Series Design Guide (5,891kb)
Series S1X70000Series
Features
  • High-density integration (0.18 μm CMOS process technology using 3/4/5/6-layer interconnect process, number of raw gates: 5,300,000 Max.)
  • High-speed operation (Internal gate delay: 43.6ps/1.8V, 2-input NAND Typ.)
  • Selectable supply voltage: Operation on single power supply (1.8V, 1.5V),
    Operation on dual power supply (I/O: 3.3V/internal: 1.8V, I/O: 2.5V/internal: 1.8V, I/O: 3.3V/internal: 1.5V, I/O: 2.5V/internal: 1.5V)
  • Lower power consumption (Internal cell: 0.077 μW/MHz/gate, 1.8V, Typ.)
  • Drivability (IOL = 2, 4, 8, 12mA at 3.3V, IOL = 1.5, 3, 6, 9mA at 2.5V, IOL = 1, 2, 4, 6mA at 1.8V, IOL = 0.75, 1.5, 3, 4.5mA at 1.5V)
Macro Cells RAM, ROM, MCU, PLL, LVDS, RSDS, and various types of macro cells can be implemented
Package 48-pin to 256-pin QFP, PBGA, PFBGA, QFN
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S1X60000Series

Status MP
Manual S1X60000 Series Design Guide (3,354kb)
Series S1X60000Series
Features
  • High-density integration (0.25 μm CMOS process technology and 3/4/5-layer interconnect process, number of raw gates: 2,500,000 Max.)
  • High-speed operation (Internal gate delay: 107 ps/2.5 V, 2-input power NAND Typ.)
  • Selectable supply voltage: Operation on a single power supply (2.0 V, 2.5 V)
    Operation on dual power supply (I/O: 3.3 V/internal: 2.5 V, I/O: 3.3 V/internal: 2.0 V)
  • Low power consumption (Internal cell: 0.18 μW/MHz/gate, 2.5V, Typ.)
  • Drivability (IOL = 0.1, 1, 3, 6, 12, 24 mA at 3.3 V, IOL = 0.1, 1, 3, 6, 12, 24 mA at 2.5 V, IOL = 0.05, 0.3, 1, 2, 4, 8 mA at 2.0 V)
Macro Cells RAM, ROM, Flash, MCU, PLL, LVDS, RSDS, and various types of macro cells can be implemented
Package 48-pin to 256-pin QFP, PBGA, PFBGA, QFN
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S1X50000Series

Status MP
Series S1X50000Series
Features
  • High-density integration (0.35 μm CMOS process technology and 3/4-layer interconnect process)
  • High-speed operation (Internal gate delay: 140 ps/3.3 V, 2-input power NAND Typ.)
  • Selectable supply voltage: Operation on a single power supply (2.0 V, 2.5 V, 3.3 V)
    Operation on dual power supply (I/O: 5.0 V/internal: 3.3 V, I/O: 3.3 V/internal: 2.5 V, I/O: 3.3 V/internal: 2.0 V)
  • Low power consumption (Internal cell: 0.39 μW/MHz/gate, 3.3V, Typ.)
  • Drivability (IOL=0.1, 1, 3, 8, 12, 24 mA at 5.0 V, IOL=0.1, 1, 2, 6, 12 mA at 3.3 V, IOL=0.1, 0.5, 1, 3, 6 mA at 2.5 V, IOL=0.05, 0.3, 0.6, 2, 4 mA at 2.0 V)
Macro Cells RAM, ROM, Flash, MCU, PLL, analog cells, LVDS, RSDS, and various types of macro cells can be implemented
Package 48-pin to 256-pin QFP, PBGA, PFBGA, QFN, WCSP
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