Libraries generated by the "G/A RAM Library Generation Tool"

1. Libraries to be generated

The G/A RAM library generation tool generates the following libraries:

(1)Libraries for RTL simulation ( _rtl.lib, _rtl.vhd)

Libraries for the RTL simulation of Epson's gate array synchronous RAMs.
The file name for Verilog description is "(RAM cell name)_rtl.lib" and that for VHDL description is "(RAM cell name)_rtl.vhd".

(2) Bus wrapper examples ( _wrp.v, _wrp.vhd )

It takes time to connect the RAM models discussed in (1) above because their input and output pins are not described in bus format. To cope with this problem, a bus wrapper, a module that converts a set of pins to a bus description, is offered. However, the use of the module adds one more level to the existing design hierarchy. Though the use of the bus wrapper module is not a must, if used, please send it to Epson together with your RTL description files.

The module name is "(RAM cell name)_wrp". The file name for Verilog description is "(RAM cell name)_wrp.v" and that for the VHDL description is "(RAM cell name)_wrp.vhd".

(3) Logic synthesis module (only for the S1L50000 series)

The S1L50000 series synchronous RAMs are a soft macro composed of asynchronous RAM, D-FF, and some gates. The soft macro is generated by synthesizing this module. When performing logic synthesis, please refer to Section 3-2, and synthesize this file as well as your RTL files.

If you leave the task of logic synthesis to Epson, please send this module file together with the RTL description files to Epson. description is "(RAM cell name)_syn.vhd".

The file name of Verilog description is "(RAM cell name)_syn.lib" and that of VHDL description is "(RAM cell name)_syn.vhd".

2. Notes

The following are the general notes on the RAM libraries:

  • For the functions of RAMs of other series than S1L50000, refer to the respective Design Guides. For the S1L50000 series RAM functions, refer to Section 3 of this document.
  • Library models for the RTL simulation are simplified; thus they do not fully reflect the behaviors of actual components. Sufficient verification by running delay simulation is strongly recommended.
  • If data is written when the address is X (unknown), data held in all the addresses become unknown (X).
  • hen the control signal goes X, X is written to the input address in the write operation, if it occurs.

3. S1L50000 series synchronous RAM

The S1L50000 series synchronous RAMs are soft macros. Each RAM is a macro in the RTL file, and handled as a soft macro in logic synthesis and subsequent design steps.

3.1 Notes on simulation and behaviors

The following are the notes on the simulation and behaviors of S1 S1L50000 series synchronous RAMs:

  • If the Chip Select (XCS) of the 1-port synchronous RAM and the Read Enable (XRB) of 2-port synchronous RAM are set inactive (driven high), output data is not held. (The output becomes X (unknown) in simulation.)
  • When simultaneously writing and reading to and from the same address in the synchronous 2-port RAM, it is possible to read the written data within the same cycle. However, care must be taken for that the read access time differs from the normal operation. (Refer to Section 3-11.)
  • If new data is written to a latched read address (AB*) of the 2-port RAM when the read clock (CKB) is disabled, note that the new data is read. This is because the structure not to latch the output data.
  • The RAMs are soft macros, and therefore, the timing changes after the place and route.
  • Forcible Chip Select (FCS) is a dedicated test pin. Set FCS to high for normal operation. The RTL simulation models are described to behave correctly only when FCS is set to high. For example, if the RAM enters write state when FSC goes low, and then FCS changes to high in the same state, the RAM may perform write operation depending on timing conditions. However, this never happens to the RTL simulation models.

3.2 Notes on logic synthesis

Pay attention to the following points when synthesizing the RTL code including the S1L50000 series synchronous RAM:

  • The S1L50000 series gate array are described in the logic synthesis module discussed in Step 1-(3) above; thus specify the S1L50000 series library for the link_library command.

    e.g. set link_library { * s1l50000_33v.db }

  • The "DL2" delay cell is included in the logic synthesis module discussed in Step 1-(3) above; specify the dont touch command not to loose the cell by logic reduction.

    e.g. set_dont_touch s1l50000/DL2

  • Read the logic synthesis module discussed in Step 1-(3) above (_syn.v or _syn.vhd) together with other RTL source files.

    e.g. read_verilog SK06008X_syn.v

3.3 Outline

The following describes the outline of the S1L50000 series synchronous RAMs:

  • There are 1-port and 2-port type synchronous RAMs. The 2-port synchronous RAM has port A only for writing and port B only for reading.
  • The range of configurable word depth is from 8 to 256 words in increments of 4 words. The range of configurable word width is from 1 to 32 bits in increments of 1 bit. However, access to a non-existent address of the internal asynchronous RAM (for example, access to address 94 of 94-word RAM) is prohibited. If such access is likely to occur, use multiple RAMs whose word depth is a power of 2.

3.4 Word-bit configuration and cell names

The S1L50000 series synchronous RAM cell names are determined by the sizes as explained below.

  • 1-port synchronous RAM cell name : SJwwwbbX
  • 2-port synchronous RAM cell name: SKwwwbbX

Where www are 3 hexadecimal digits indicating the word depth (word count);
and bb are 2 hexadecimal digits indicating the word width (bit count).

Table 1. Examples of 1-port RAM cell names

Width / Depth 32 Word 64 Word 128 Word 256 Word
8 bit SJ02008X SJ04008X SJ08008X SJ10008X
10 bit SJ0200AX SJ0400AX SJ0800AX SJ1000AX
16 bit SJ02010X SJ04010X SJ08010X SJ10010X
32 bit SJ02020X SJ04020X SJ08020X SJ10020X

Table 2. Examples of 2-port RAM cell names

Width / Depth 32 Word 64 Word 128 Word 256 Word
8 bit SK02008X SK04008X SK08008X SK10008X
10 bit SK0200AX SK0400AX SK0800AX SK1000AX
16 bit SK02010X SK04010X SK08010X SK10010X
32 bit SK02020X SK04020X SK08020X SK10020X

3.5 Basic cell count

The basic cell count (BC count) of the S1L50000 series synchronous RAM cell is that of the asynchronous RAM cell and the additional circuitry as shown below. For the asynchronous RAM cell size, refer to the S1L500000 Series Design Guide.

  • The size of additional circuitry to the 1-port synchronous RAM

    ((Address pin count) + (word width) x 2) x (BC count of D-FF) + 13 [BC]

  • The size of additional circuitry to the 2-port synchronous RAM

    ((Address pin count) x 2 + (word width) x 2) x (BC count of D-FF) + 13 [BC]

For the BC count of D-FF, refer to the S1L50000 series MSI library. For rough estimation, use 10 BCs of the low-noise type scan-FF.

3.6 1-port synchronous RAM pin description

Table 3 describes the 1-port synchronous RAM pins.

Table 3. 1-port synchronous RAM pin description

Pin name Signal name Description
CK Clock input RAM latches input signals other than FCS at the rising edge (L ->H) of this clock input (CK)
XCS Chip select input RAM goes active when low value is latched by CK. If the latched value is high, Y* outputs become unknown and previous data is not held.
XWE Write enable input RAM writes data when the value latched by CK is low; and reads when high.
A0 ～ An Address input Address input pins
D0 ～ Dn Data input Write data input pins
Y0 ～ Yn Data output In read operation, RAM outputs read data after the access time from the rising edge of CK. In write operation the first half of the cycle is unknown, and data written in the latter cycle is read.
FCS Forcible chip select input Used to forcibly disable the asynchronous RAM when testing. For normal operation, set this pin to high.

3.7 1-port synchronous RAM configuration diagram

The 1-port synchronous RAM is configured with 1-port asynchronous RAM, D-FF, and gates.

3.8 1-port synchronous RAM timing specification

Figures 2 and 3 are timing diagrams of the 1-port synchronous RAM; and Table 4 shows the timing data.

Table 4. 1-port synchronous RAM timing data

Name Symbol Description
Access time tACS (D-FF delay) + (Asynchronous RAM access time)
Input signal setup time tSI D-FF setup time
Input signal hold time tHI D-FF hold time
Output hold time tHO (D-FF delay) + (Asynchronous RAM output hold time)
Clock high pulse width tWH (Asynchronous RAM write pulse width) + (Margin)
Read delay after write tDWR (Asynchronous RAM RW access time) + (DL2 delay) + (OR21 delay)

3.9 2-port synchronous RAM pin description

Table 5 describes 2-port synchronous RAM pins.

Table 5. 2-port synchronous RAM pin description

Pin name Signal name Description
CKA Clock A input Clock input for port A (port for write). RAM latches the input signals at port A (XWA, AA* and D*) at the rising edge (L->H) of this clock input (CKA)
XWA Write enable input RAM writes when the value latched by CKA is low
AA0 ～ AAn Write address input Address input pins for write port
D0 ～ Dn Data input Write data input pin
CKB Clock B input Clock input for port B (port for read). RAM latches the input signals at port B (XRB and AB*) at the rising edge (L->H) of this clock input (CKB)
XRB Read enable input RAM reads when the value latched by CKB is low. Care must be taken for that Y* outputs become unknown (the previous data is not held), when this input is high.
Y0 ～ Yn Data output In read operation, read data is output after the access time from the rising edge of CKB.
FCS Forcible chip select Used to forcibly disable the asynchronous RAM when testing. For normal operation, set this pin to high.

3.10 2-port synchronous RAM configuration diagram

The 2-port synchronous RAM is configured with 2-port asynchronous RAM, D-FF, and gates.

3.11 2-port synchronous RAM timing specification

Figures 5 and 6 are timing diagrams of the 2-port synchronous RAM; and Table 6 shows timing data.

Table 6. 2-port synchronous RAM timing data

Name Symbol Description
Access time tACS (D-FF delay) + (Asynchronous RAM access time)
Input signal setup time tSI D-FF setup time
Input signal hold time tHI D-FF hold time
Output hold time tHO (D-FF delay) + (Asynchronous RAM output hold time)
Clock high pulse width tWH Asynchronous RAM write pulse width + margin
Read delay after simultaneous write to the same address tDWR (DL2 delay) + (IN1 delay) + (NO2 delay + (Asynchronous RAM access time) in relation to CKA

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